Current upstream glibc reports all-zero for cache size information on Intel TDX (at least in Azure TDX implementation; Intel's KVM port reportedly behaves similarly though).

This may need a fix within glibc. I started an upstream discussion:

Missing cache information on x86-64 under Intel TDX (glibc bug 30643)
<https://inbox.sourceware.org/libc-alpha/87mszv7x0l.fsf@oldenburg.str.redhat.com/>

This is related to Red Hat bug 2177705, which contains an incomplete fix attempt.